1. SPECIAL COMMANDS

1.1. Status

Direction	Data	Description
Tx transmit	‘TT’	ASCII character ‘T’ repeated twice
Rx receive	‘TT’ + 10 status bytes	see the description of the status record total number of bytes to receive: 12 bytes

Direction	Data	Description
Tx	‘??’
Rx	byte1 byte2	State (see the description of the State record) ErrCode total number of bytes to receive: 2 bytes (’??’ not echoed!):

Direction	Data	Description
Tx	‘Q’	once only!
Rx	’Q’ ’T’ ’E’ ’Y’ or none	one of the following: ok to communicate expecting the status (’T’) command error, send ’T’ to cancel error ﬂag busy

run	R
stop	S
normal burst	G
burst and invert all waveforms	B
end of data transfer	F (ends L, W, M commands)

Tx Data	Size	Description
‘L’	byte	ASCII character ‘L’
‘L’	byte (repeated)
select	byte	designated channels; ‘1’ at bit position selects the channel
select	byte (repeated)	b0 = channel1,…,b7 = channel8; all ‘0’ = timing
count	word	= number of data words to follow; HiAddr = count-1
data	word
data	word
……	words
		undeﬁned length (at least 8 bytes)

Download one by one (timing and all waveforms) and then send ‘F’ command.

Tx Data	Size	Description
‘W’	byte
‘W’	byte
select	byte	designated channels; ‘1’ at bit position selects the channel
select	byte	b0 = channel1,…,b7 = channel8; all ‘0’ = timing
count	word	= number of data words to follow; HiAddr = count-1
data	word
data	word
……	words
		undeﬁned length (at least 8 bytes)

Download one by one (timing and all waveforms) and then send ‘F’ command.

For large number of data to be sent (>24k) stop the generator ﬁrst, download and restart.

Tx Data	Size	Description
‘D’	byte
‘D’	byte
select	byte	designated channels; ‘1’ at bit position selects the channel
select	byte	b0 = channel1,…,b7 = channel8; all ‘0’ = timing
address	word	deﬁned as offset from memory start as: (pulse number)*2-2
data	word	amplitude or pulse-width
		undeﬁned length (at least 8 bytes)

Tx Data	Size	Description
‘M’	byte
‘M’	byte
select	byte	designated channels; ‘1’ at bit position selects the channel
select	byte	b0 = channel1,…,b7 = channel8; all ‘0’ = timing
address	word	deﬁned as offset from memory start as: (pulse number)*2-2
data	word
		undeﬁned length (at least 8 bytes)

Tx Data	Size	Description
‘C’	byte
‘C’	byte
data	word
		undeﬁned length (at least 8 bytes)

Tx Data	Size	Description
‘U’	byte
‘U’	byte
theClock Choice	byte	see Setup codes
theMode	byte	see Setup codes
		total length of the command: 4 bytes

Tx Data	Size	Description
‘X’	byte
‘X’	byte
start address	word	inclusive, deﬁned as offset (see ’D’ cmd)
pulse count	word
		total length of the command: 6 bytes

Tx Data	Size	Description
‘I’	byte	ASCII character, capital ‘i’
‘I’	byte
before address	word	inclusive, deﬁned as offset (see ’D’ cmd)
pulse count	word
		total length of the command: 6 bytes

Tx Data	Size	Description
‘Z’	byte	ASCII character, capital ‘i’
‘Z’	byte
select	byte	designated channels; ‘1’ at bit position selects the channel
select	byte	b0 = channel1,…,b7 = channel8; all ‘0’ = timing
start address	word	inclusive, deﬁned as offset (see ’D’ cmd)
pulse count	word
		total length of the command: 8 bytes

Tx Data	Size	Description
‘O’	byte	ASCII character, capital ‘o’, not ‘zero’
‘O’	byte
select	byte	designated channels; once only
direction	byte	Boolean; right = TRUE, left = FALSE(0)
step count	word
		total length of the command: 6 bytes

Tx Data	Size	Description
‘V’	byte	ASCII character, capital ‘o’, not ‘zero’
‘V’	byte
select	byte	designated waveform; one at a time only;
select	byte	designation of timing not allowed
start address	word	inclusive, deﬁned as offset (see ’D’ cmd)
pulse count	word	-1 means ’all’
		total length of the command: 8 bytes

The status record contains 10 bytes.

Byte 1	Variable	Meaning
b0	XCLK	monitors the external clock
b1	XTRG	monitors external start/stop signal
b2	START	control signal (as placed by the microprocessor)
b3	MEM	swap control: =0 CPU accesses RAM1 and scanning counter <-> RAM2, (as placed by the microprocessor)
b4	RST	extended reset signal (as placed by the microprocessor)
b5	XI	external/internal time-base clock choice (see below)
b6	FS	external/internal time-base clock choice (see below)
b7	SOFTCK	software generated time-base output
Byte 2	Variable	Meaning
b0…5		not implemented
b6	CLEAR	monitors the real state of RUN/STOP, =0 running, =1 stopped
b7	SWAP	monitors which RAM is being scanned for output (cf. MEM bit above)
Byte	Content	Description
Byte 3	Card Mask	bit b0…7 set if the corresponding output channel is installed and working properly
Byte 4	Ready Flag	if <>0 then the generator may accept the RUN command
Byte 5,6	HiAddr	highest occupied RAM address
Byte 7	model	2 or 8-channel model
Byte 8	decimal value	ﬁrmware revision
Byte 9	State message	Meaning
b0	XCLK	monitors the external clock
b1	XTRG	monitors external start/stop signal
b2	START	control signal (as placed by the microprocessor)
b3	MEM	swap control: =0 CPU accesses RAM1 and scanning counter <-> RAM2, (as placed by the microprocessor)
b4	RST	extended reset signal (as placed by the microprocessor)
b5	XI	external/internal time-base clock choice (see below)
b6	FS	external/internal time-base clock choice (see below)
b7	SOFTCK	software generated time-base output

Constant	Value	Meaning
kStopped	0	all bits must be 0
kRunning	1
kRunOut	2	STOP command received, ﬁnishing the waveform
kWaitSwap	4	one memory bank has been updated and WFG is waiting for the end of waveform to swap the memory banks and gain access to the other memory bank
kBurst	8	the single burst mode is selected
kPanel	16	external triggering selected
kUndeﬁned	32
kArmed	64	ready to run
kExpectingData	128	current communication not completed

theMode	Hex value	Meaning
codeBurst	0x04	burst / continuous mode
codePane	0x08	enable external triggering
theClockChoice	Hex value	Meaning
codeEclock	0x60	20 MHz internal clock
codeE2clock	0x20	1 MHz internal clock
codeSoft	0x40	software-controlled internal clock (slow)
codeExt	0x00	external clock